Variation in performance and power across manufactured parts and their operating conditions is an accepted reality in aggressive CMOS processes. This paper considers challenges and opportunities in identifying this variation and methods to combat or even use these variations for improved computing systems. We introduce the notion of instruction-level vulnerability (ILV) and concurrent instruction reuse (CIR) to expose variation and its effects to the software stack for use in architectural and runtime optimizations. Going further up on the hardware-software stack, we also introduce the notion of tasklevel vulnerability (TLV) as metadata to characterize dynamic variations. In fact, TLV is a vertical abstraction that reflects manifestation of circuit-level hardware variability in specific software context for parallel execution model.
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