An Efficient FPGA Implementation of Scalable Matrix Inversion Core using QR Decomposition

Ali Irturk, Shahnam Mirzaei and Ryan Kastner
CS2009-0938
March 9, 2009

We present a novel scalable architecture for matrix inversion that uses the modified Gram-Schmidt algorithm based on QR decomposition. Our core achieves a throughput of 0.18M updates per second for a 4 x 4 matrix using 19 bits of precision on a Xilinx Virtex4 SX FPGA. We also present two different designs which use longer data lines, 26 and 32 bits, and compare our results with another matrix inversion architecture which is the only scalable approach so far. We show that our core is significantly faster than the other published FPGA implementation as it requires fewer resources due to the usage of fixed point arithmetic and an effective resource utilization. We show that our proposed architecture is scalable by presenting the results for 6 x 6 and 8 x 8 matrices.


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