FPGA Implementation of Adaptive Weight Calculation Core Using QRD-RLS Algorithm

Ali Irturk, Shahnam Mirzaei and Ryan Kastner
March 9, 2009

We present a novel architecture for adaptive weight calculation (AWC) that uses the QR decomposition based recursive least squares (RLS) algorithm. Our AWC core achieves a throughput of 0.20M updates per second for a 4 x 4 matrix on a Xilinx Virtex4 SX FPGA. We show that our core is significantly faster than other published FPGA implementations and it requires fewer resources. This is largely a consequence of careful error analysis that allows us to take advantage of a fixed point data representation with little degradation in the final results. Finally, our proposed architecture scales well for larger size matrices.

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