Statistical timing analysis is based on a priori knowledge of process variations. The lack of such a priori knowledge of process variations prevents accurate statistical timing analysis and has been largely blamed for foundry confidentiality policy. In this paper, we show that a significant part of process variations are specific to the design, and can only be achieved based on production chip performance variabilities. We adopt the homogeneous isotropic random field model for intra-die random variations, apply fast Fourier transform (FFT) to simulate a homogeneous isotropic random field, obtain corners for Monte Carlo SPICE simulation of timing critical paths in a VLSI circuit, and apply regression to match production chip performance variability. Our experimental results based on a timing critical path in an industry design with 70nm Berkeley Predictive Technology Models reveal constant mean, increased standard deviation, and decreased skewness of a signal propagation path delay as spatial correlation increases. Our proposed spatial correlation extraction technique can be applied in a chip tapeout process, where process variations extracted from an early tapeout help to improve statistical timing analysis accuracy and guide engineering change order for subsequent tapeouts.
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