We observe that Monte Carlo (SPICE) simulation provides the most accurate and trustable statistical timing analysis, while the existing SSTA method has completely ignored the effect of input statistics on chip timing performance, and provides either accurate estimate nor pessimistic bound of the actual chip timing performance statistics. We propose signal probability (i.e., the logic one occurrence probability for a signal) based statistical timing analysis for improved accuracy and reduced pessimism over the existing SSTA methods, and improved efficiency over Monte Carlo (SPICE) simulation. Our experimental results show that our proposed SPSTA computes mean (standard deviation) of signal arrival times within 6.2% (18.6%), while SSTA computes mean (standard deviation) of signal arrival times within 13.40% (64.3%) of Monte Carlo simulation results; SPSTA also provides signal probaiblity estimation within 14.28% of Monte Carlo simulation results for the ISCAS'89 benchmark circuits.
The authors of these documents have submitted their reports to this technical report series for the purpose of non-commercial dissemination of scientific work. The reports are copyrighted by the authors, and their existence in electronic format does not imply that the authors have relinquished any rights. You may copy a report for scholarly, non-commercial purposes, such as research or instruction, provided that you agree to respect the author's copyright. For information concerning the use of this document for other than research or instructional purposes, contact the authors. Other information concerning this technical report series can be obtained from the Computer Science and Engineering Department at the University of California at San Diego, firstname.lastname@example.org.
[ Search ]