A gate output signal transition in DSM designs is approximated in a ramp function followed by an exponential attenuation tail. We observe that an "effective capacitance" is the gate output charge during the ramp signal transition time at the gate output with a unit supply voltage. We propose a tail approximation scheme which matches the "remaining capacitance", s.t., the total gate output charge equals the total load capacitance with a unit supply voltage. We model a driving point signal transition in a piecewise linear-and-exponential (PWLE) function in accordance with the saturation and the linear behaviors of a driving transistor. We present tail approximation and interconnect delay calculation formulas with PWLE functions. Our experimental results from industry design test cases show an average of 3.8%(8.6%) and maximum of 15.4%(16.7%) accuracy improvement over existing ramp-based driving point signal transition approximation schemes in interconnect delay (transition time) calculation.
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