Wirelength estimation techniques typically contain a site density function and an occupation probability function. SOC designs contain large IP blocks which form routing obstacles and deviate wirelength estimation. In this paper, we extend previous work of wirelength estimation in the presence of obstacles by considering feedthrough channel effect and derive complete expressions in the presence of two obstacles. Our results are one step further into the domain of wirelength estimation in the presence of multiple obstacles and towards finding the equavalent obstacle relations to facilitate a priori wirelength estimation schemes in chip planning tools, i.e., wireload models to improve parasitic estimation accuracy and timing closure.
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