Enhanced Design Flow and Optimizations for Multi-Project Wafers

Andrew Kahng, Ion Mandoiu, Xu Xu and Alex Zelikovsky
CS2005-0823
May 14, 2005

The aggressive scaling of VLSI feature size and the pervasive use of advanced reticle enhancement technologies leads to dramatic increases in mask costs, pushing prototype and low volume production designs at the limit of economic feasibility. Multiple project wafers (MPW), or "shuttle" runs, provide an attractive solution for such designs, by providing a mechanism to share the cost of mask tooling among up to tens of designs. However, MPW reticle floorplanning and wafer dicing introduce complexities not encountered in typical, single-project wafers. Recent works attempting to address these challenges have several drawbacks, including (i) assuming equal production volume requirement for all designs, (ii) assuming that the same dicing plan in used for all wafers or for all rows/columns of reticle images on a wafer, (iii) assuming unrealistic wafer models such as a rectangular array of projections, and (iv) disregarding important practical constraints on the maximum reticle size. In this report we propose a comprehensive MPW flow aimed at minimizing the number of wafers needed to fulfill given die production volumes. Our flow includes three main steps: (1)multi-project reticle floorplanning, (2) wafer shot-map definition, and (3) wafer dicing plan definition. For each of these steps we propose improved algorithms as follows. Our reticle floorplanner uses hierarchical quadrisection combined with simulated annealing to generate ``diceable'' floorplans observing given maximum reticle sizes. The new wafer shot-map definition step allows to fully utilize round wafer real estate by extracting the maximum number of functional dies from both fully and partially printed reticle images. Finally, our dicing planner allows multiple side-to-side dicing plans for different wafers as well as different reticle projection rows/columns within a wafer, and further improves dicing yield by partitioning each wafer into a small number of parts before individual die extraction. Experiments on industry testcases show that our methods outperform significantly not only previous methods in the literature, but also reticle floorplans manually designed by experienced engineers.


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