A Placement Methodology for Global Interconnect Reduction and Its Impact on Performance

Andrew Kahng, Igor Markov and Sherief Reda
CS2004-0801
October 31, 2004

Global interconnects are a bottleneck in today's high-performance deep-submicron designs. In this paper, we propose a modification to the top-down min-cut placement algorithm to reduce the number of global interconnects. Our method is generic and does not involve any timing analysis during or prior to placement. In essence, we skew the netlength distribution produced by a min-cut placer so as to reduce the number of long nets, with minimal impact on the overall wirelength. Empirically, this approach has negligible impact on placement runtime, but leads to a significant reduction in the number of global interconnects. The fewer interconnects translate to about 25% savings in the number of buffers required for signal integrity and electrical sanity, and also improve timing as measured by the worst negative slack and total negative slack of industrial benchmarks by up to 70% compared to a traditional min-cut placement flow (e.g., Capo 8.7).


How to view this document


The authors of these documents have submitted their reports to this technical report series for the purpose of non-commercial dissemination of scientific work. The reports are copyrighted by the authors, and their existence in electronic format does not imply that the authors have relinquished any rights. You may copy a report for scholarly, non-commercial purposes, such as research or instruction, provided that you agree to respect the author's copyright. For information concerning the use of this document for other than research or instructional purposes, contact the authors. Other information concerning this technical report series can be obtained from the Computer Science and Engineering Department at the University of California at San Diego, techreports@cs.ucsd.edu.


[ Search ]


NCSTRL
This server operates at UCSD Computer Science and Engineering.
Send email to webmaster@cs.ucsd.edu