The Y-architecture: Yet Another On-Chip Interconnect Solution

Hongyu Chen, Feng Zhou and Chung-Kuan Cheng
CS2002-0717
August 7, 2002

In this paper, we propose a new on-chip interconnect scheme called Y-architecture, which can utilize the on-chip routing resources more efficiently than traditional Manhattan Interconnect Architecture by allowing wires routed in three directions (0กใ, 60กใ, and 120กใ). To evaluate the efficiency of different interconnect architectures, we assume mesh structures with uniform communication demand for communication and develop a multi-commodity flow (MCF) approach to model the on-chip communication traffic. The throughput of mesh structure is used to measure the communication capabilities of different interconnect architectures. We also extend the combinatorial MCF algorithm in [5] to compute the optimal routing resource allocations for different interconnect architectures. The experiments show that: (1) Compared with Manhattan architecture, the Y-architecture demonstrates a throughput improvement of 30.7% for square chip. The throughput of meshes using Y-architecture is only 2.5% smaller than that of meshes using more complicated X-architecture. (2) A chip with the shape of a convex polygon produces better throughput than a rectangular chip: For Y-architecture, a hexagonal chip provides 41% more throughput than a squared chip using the Manhattan architecture. For X-architecture, an octagonal chip produces 31% more throughput than a squared chip using the Manhattan architecture. For Manhattan architecture, a diamond chip achieves a throughput improvement of 19.5% over the squared chip using the same interconnect architecture. (3) Compared with Manhattan architecture, the Y-architecture reduces the wire length of a randomly distributed two pin net by 13.4% and the average wire length of Y-architecture is only 4.3% more than that of the X-architecture


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